In many integrated circuit applications, a highly resistive load is needed to implement the circuit. One such example is a static RAM (SRAM) circuit. Of particular importance, the 4-transistor, 2-resistor SRAM cell (4T-2R cell) requires a resistive load in the gigaohm range.
Resistive loads in the gigaohm range are difficult to fabricate. One such method of forming a gigaohm resistive load requires a polysilicon deposition which is dedicated solely to forming the load resistors. Consequently, several steps, including at least one masking step, are required solely for the formation of the gigaohm resistors. As a general rule, each masking step increases the complexity of the fabrication process, and reduces the yield due to the increased likelihood of misalignment. This increased complexity is particularly troublesome in high density circuits such as SRAM memory cells.
Often, memory cells arrays are made using a CMOS or bipolar process which implements either all bipolar or all CMOS devices in a single integrated circuit. BiCMOS processes tend to be less efficient in the number of steps than either a bipolar only or CMOS only process. Therefore, it is particularly important in a BiCMOS process to reduce the number of steps and the number of masks in order to optimize fabrication of the circuit.
Therefore, a need has arisen to provide a highly resistive load which requires minimal additional steps, particularly in connection with a BiCMOS process.